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Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
FEATURES
* (2) LVCMOS/LVTTL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK * Output frequency range: 15.625MHz - 350MHz * Crystal input frequency range: 12MHz to 40MHz * VCO range: 250MHz to 700MHz * Parallel or serial interface for programming counter and output dividers * RMS period jitter: 30ps (maximum) * Cycle-to-cycle jitter: 100ps (maximum) * Full 3.3V or mixed 3.3V core/2.5V output supply voltage * -40C to 85C ambient operating temperature * Lead-Free fully RoHS compliant
GENERAL DESCRIPTION
The ICS8402I is a general purpose, Crystal-toLVCMOS/LVTTL High Frequency Synthesizer and HiPerClockSTM a member of the HiPerClockS TM family of High Performance Clock Solutions from ICS. The ICS8402I has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8402I make it an ideal clock source for Gigabit Ethernet and SONET applications.
ICS
BLOCK DIAGRAM
OE0 OE1 VCO_SEL
PIN ASSIGNMENT
VCO_SEL nP_LOAD XTAL_IN
M4
32 31 30 29 28 27 26 25 XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT
1 0
M3
M2
M1
M0
M5 M6 M7 M8 N0 N1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST
24 23 22
XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
ICS8402I
21 20 19 18 17
PLL
PHASE DETECTOR
MR
nc GND
/2 /4 /8 /16
Q0
/M
1
Q1
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
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1
VDDO
VDD
VCO
REV. A DECEMBER 23, 2004
GND
OE1
OE0
Q1
Q0
0
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
put divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 M 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8402I features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVCMOS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8402I support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N out-
T1 0 0 1 1
T0 0 1 0 1
TEST Output LOW Shift Register Output Output of M divider CMOS Fout
SERIAL LOADING
S_CLOCK
S_DATA
t
T1
S
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8402AYI
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Input Power Output Pullup Pullup M divider inputs. Data latched on LOW-to-HIGH transition Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Power supply ground. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. Core supply pin. Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are in Tri-State. See Table 3D, OE Function Table. LVCMOS / LVTTL interface levels. Output supply pin. Clock outputs. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Pullup Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc GND TEST VDD OE1, OE0 VDDO Q1, Q0
17
MR
Input
Pulldown
18 19 20 21 22 23 24, 25 26 27
S_CLOCK S_DATA S_LOAD VDDA XTAL_SEL TEST_CLK XTAL_OUT, XTAL_IN nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pulldown Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
Test Conditions VDD, VDDA, VDDO = 3.465V VDD, VDDA = 3.465V, VDDO = 2.625V Minimum Typical 4 13 11 51 51 VDDO = 3.465V VDDO = 2.625V 5 7 7 12 Maximum Units pF pF pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs MR H L L L L L L L nP_LOAD X L H H H H H M X Data Data X X X X X N X Data Data X X X X X S_LOAD X X L L L H S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. Conditions
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
256 M8 0 0 * * 0 0 0 128 M7 0 0 * * 0 0 0 64 M6 0 0 * * 0 0 0 32 M5 0 0 * * 0 0 0 16 M4 0 0 * * 1 1 1 8 M3 1 1 * * 1 1 1 4 M2 0 0 * * 0 0 1 2 M1 1 1 * * 1 1 0 1 M0 0 1 * * 0 1 0
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 250 275 * * 650 675 700 M Divide 10 11 * * 26 27 28
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 2 4 8 16 N Divider Value Output Frequency (MHz) Minimum Maximum 125 62.5 31.25 15.625 350 175 87.5 43.75
TABLE 3D. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE
Control Inputs OE0 0 0 1 1 OE1 0 1 0 1 Q0 Hi-Z Hi-Z Enabled Enabled Output Q1 Hi-Z Enabled Hi-Z Enabled
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 Maximum 3.465 3.465 3.465 2.625 125 18 10 Units V V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter Input High Voltage VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, OE0, OE1, XTAL_SEL, VCO_SEL M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, OE0, OE1, XTAL_SEL, VCO_SEL Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDO = 3.465V VDDO = 2.625V -5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A
VIH
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
-150 2.6 1.8 0.5
A V V V
VOH VOL
8402AYI
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2.
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6
REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 12 12 Typical Maximum 40 40 Units MHz MHz
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL_IN XTAL_OUT NOTE 1
S_CLOCK 50 MHz NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 M 58. Using the maximum frequency of 40MHz, valid values of M are 7 M 17.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance (CO) 12 Test Conditions Minimum Typical Maximum 40 50 7 Units MHz pF Fundamental
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle 300MHz 20% to 80% 0.25 5 5 5 5 5 5 40 60 Test Conditions Minimum 15.625 40 8 Typical Maximum 350 100 30 80 1.1 Units MHz ps ps ps ns ns ns ns ns ns ns %
tjit(cc) tjit(per) tsk(o)
tR / tF
PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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7
REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 15.625 40 Typical Maximum 350 100 30 60 20% to 80% 0.25 5 5 5 5 5 5 300MHz 40 60 1.0 Units MHz ps ps ps ns ns ns ns ns ns ns %
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD tS Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle
tjit(cc) tjit(per) tsk(o)
tR / tF
PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VDD, VDDA VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VOH VREF
V
DDO
Qx
2
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
V
DDO
Qy
2 tsk(o)
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
OUTPUT SKEW
V V V
PERIOD JITTER
80% 20% tR tF 80% 20%
DDO
DDO
DDO
Q0, Q1
2
2
2
tcycle n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
V
DDO
Q0, Q1
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8402AYI
2
tcycle n+1
Clock Outputs
OUTPUT RISE/FALL TIME
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9
REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8402I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8402I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN
C1 22p
X1 18pF Parallel Cry stal
XTAL_OUT
C2 22p
ICS8402I ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
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REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8402I is: 3784
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11
REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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12
REV. A DECEMBER 23, 2004
Integrated Circuit Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
Marking ICS8402AYI ICS8402AYI TBD TBD Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQPF on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8402AYI ICS8402AYIT ICS8402AYILF ICS8402AYILFT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8402AYI
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REV. A DECEMBER 23, 2004

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